| A Design of High Performance Parallel CRC Generator |
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Hyun bean Yi;Sung ju Park;Pyoung woo Min;Chang won Park |
| 고성능 병렬 CRC 생성기 설계 |
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이현빈;박성주;민병우;박창원 |
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| Abstract |
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This paper presents an optimization algorithm and technique for designing parallel Cyclic Redundancy Check (CRC) circuit, which is most widely adopted for error detection A new heuristic algorithm is developed to find as many shared terms as possible, thus eventually to minimize the number and level of the exclusive-or logic blocks in parallel CRC circuits. 16-bit and 32-bit CRC generators are designed with different types of Programmable Logic Devices, and it has been found that our new algorithm and architecture significantly reduce the delay. |
| Key Words:
CRC(Cyclic Redundancy Check), Parallel CRC, Logic Optimization, XOR Gate |
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